Technical field
The present disclosure relates to Dynamic Random Access Memory (DRAM) integrated Circuits (IC). Particularly, the present disclosure relates to multi-cycle write leveling in DRAM devices. More particularly, the present disclosure relates to synchronizing the clock signal and data strobe signal in a DRAM device using multi cycle write leveling procedure.
Description of the Related Art
Memory devices/systems used in computing systems typically incorporate one or more Dynamic Random Access Memory (DRAM) integrated circuits arranged on a memory module, for example, a DIMM (Dual In-Line Memory Module). A DIMM typically includes multiple DRAM devices serially mounted on a Printed Circuit Board (PCB), and is typically adapted to be used in personal computers, laptop computers, servers and the like. Typically, the operations of DRAM devices (on the DIMM) are controlled by a memory controller. Recent evolutions in the field of memory devices include DDR3 DRAM, third generation of the DDR DRAM family, which offers enhanced data bandwidth and signal quality.
To achieve enhanced signal integrity at higher data rates, DDR3 memory modules typically adopt fly-by signal routing for clock (CK), address, command (for example, RAS_n, CAS_n and the like) and control signals (for example, CS_n, ODT, and the like) while matching the trace length for data (DQ) and data strobe (DQS). The consequence of incorporating fly-by topology is though at the DRAM controller, wherein CK and DQS could be designed to meet the DRAM timing specification (tDQSS) as shown in FIG. 1 but at the DRAM ball the CLK and DQS are no longer in phase given the difference in the trace lengths of CK and DQS as shown in FIG. 1a. In order to overcome the aforementioned drawback, the memory controller uses a feature termed as ‘write leveling’ wherein the feedback from the DDR3 DRAM is utilized to adjust/calibrate DQS (data strobe signal) with the clock signal. A conventional method specified by Joint Electron Device Engineering Council (JEDEC) to align clock signal (CK) and data strobe (DQS) is to perform write leveling using a simple feedback mechanism from a DRAM. However, this method is efficient only when the trace difference is less than a single DRAM clock cycle. When the trace difference is greater than one DRAM clock cycle, the specified method does not accomplish cycle matching at the DRAM ball as shown in FIG. 1b. 